JP-A No. 2002-299466 is a document that discloses an insulated device isolation type bipolar transistor technique on an SOI (Silicon On Insulator) substrate. Particularly, FIG. 2 of the document shows an example of planar and cross sectional structures of a unit bipolar transistor. Further, FIG. 4 of the document shows an example of the arrangement for interconnections when multiple unit bipolar transistors are connected in parallel. Further, FIG. 21 of the document shows an example of a cross sectional structure of a multi-emitter type unit bipolar transistor.